This invention relates to insulated-gate field-effect transistor (IGFET) logic circuits and more particularly to clocked IGFET logic circuits capable of operating at very slow clock rates.
Clocked IGFET logic circuits which perform predetermined logical functions on a plurality of input signals synchronously with a system or subsystem clock are well known in the art. Generally, clocked IGFET logic circuits are dynamic and have the advantages of low power dissipation, high performance and low device count. A typical example of such a circuit includes a precharge transistor having its conduction channel connected between a V.sub.DD supply terminal and an output terminal, a functional network connected between the output terminal and a switch ground node, and a ground switch transistor having a conduction channel connected between the switch ground node and a V.sub.SS supply terminal. The functional network includes a plurality of transistors each having a gate connected to a respective one of a plurality of input signals and a conduction channel which is connected together with those of the other transistors of the functional network in a configuration which provides the circuit with the predetermined logical function. The gates of the precharge transistor and the switch ground transistor both receive control signals which are synchronous with the clock.
During a precharge phase of the clock the precharge transistor is turned ON while the ground switch transistor is turned OFF, and the output terminal is held at V.sub.DD potential which is a logic "1" level. During an active phase of the clock the precharge transistor is turned OFF while the switch ground transistor is turned ON, and the output terminal manifests a logic level which is a function of the state of the input signals. Because the precharge transistor is turned OFF, a logic "1" level at the output terminal during the active phase is maintained by the charge which is stored on the parasitic and load capacitances at that terminal. However, owing to the various charge loss mechanisms which are present at the output terminal, such as reverse pn-junction leakage at source and drain junctions and charge sharing, the stored charge diminishes with time causing the logic "1" level to decay toward a logic "0" level while the precharge transistor remains OFF. Therefore, dynamic clocked IGFET logic circuits have the problem of decaying output states which imposes a limitation on the maximum duration of the active phase of the clock.
A prior art solution to the problem of decaying output states is to provide the output terminal of a dynamic circuit with a sustaining device such as a large resistance connected between the output terminal and the V.sub.DD supply terminal for conducting a small current from the V.sub.DD supply to the output terminal to replenish charge lost through leakage and thereby maintain a stable logic "1" level. However, this prior art solution is deficient in that it requires the addition of an extra element to each circuit causing an undesirable increase in the layout area of the circuit. Furthermore, the prior art solution also increases the parasitic capacitance at the output terminal of each circuit causing an undesirable slowing of switching speed of the circuit.
Therefore, a need clearly exists for a clocked IGFET logic circuit which provides stable output states and which has power dissipation, device count, and performance comparable to that of the dynamic circuit.